RISC-V

For forty years the defense and aerospace industry has been locked into two proprietary instruction sets: x86 and ARM. Both are brilliant engineering achievements. Both are now strategic liabilities.

x86 is a 1970s museum piece carrying half a century of backward-compatibility baggage: variable-length instructions, complex addressing modes, segmented memory ghosts, and a privilege-ring model that has been the root cause of Spectre, Meltdown, and an endless parade of side-channel exploits. It is fundamentally uncertifiable at DO-178C DAL-A without heroic tool qualification and runtime mitigation layers that burn watts, cycles, and schedule.

ARM is cleaner, but it is a proprietary ISA under foreign license control. Every Cortex-M33, M55, and future M85 shipped into a U.S. weapon system, satellite, or drone carries a perpetual license encumbrance, export-control risk, and dependence on a licensor that can raise royalties, restrict availability, or revoke architectural licenses. RISC-V is different — deliberately, legally, and permanently.

• Open ISA, governed by a Swiss non-profit with U.S.-dominated board seats and U.S.-person technical steering committees. No single nation, company, or shareholder can hold it hostage.
• Clean-sheet 2010 design: fixed 32-bit instructions (or 16-bit compressed), three-operand load-store architecture, no legacy modes, no condition-code flags, no delay slots, no microcode backdoors.
• Designed from day one for static analysis, formal verification, and safety certification. Every behavior is specified; there is no “implementation-defined” escape hatch that vendors hide behind.
• Built-in extensibility that lets MRT add classified custom instructions for encrypted packet processing, constant-time crypto, or real-time sensor fusion — without paying royalties or asking permission from a foreign licensor.
• Physical memory protection (PMP) and upcoming enhanced PMP/ePMP give hard memory isolation in far fewer gates and with far less power than ARM TrustZone.
• Code density with the C extension routinely beats ARM Thumb-2 by 15–30 %, meaning smaller flash, fewer writes, longer life in radiation environments, and lower overall system cost.

And if you ever want to read some inspiring technical documentation, see the RISC-V specification at https://docs.riscv.org/reference/isa/unpriv/intro.html. Seriously - it is a rare blend of rigor, humility, and earnest desire to educate.